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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 tps65185x pmic for e ink ? vizplex ? enabled electronic paper display 1 1 features 1 ? single chip power-management solution for e ink ? vizplex ? electronic paper (e-paper) displays ? generates positive and negative gates, and source driver voltages and back-plane bias from a single, low-voltage input supply ? supports 9.7-inch and larger panel sizes ? 3-v to 6-v input voltage range ? boost converter for positive rail base ? inverting buck-boost converter for negative rail base ? two adjustable ldos for source driver supply ? tps65185 ldo1: 15 v, 120 ma (vpos) ? tps65185 ldo2: ? 15 v, 120 ma (vneg) ? tps651851 ldo1: 15 v, 200 ma at v in 3.6 v (vpos) ? tps651851 ldo2: ? 15 v, 200 ma at v in 3.6 v (vneg) ? accurate output voltage tracking ? vpos ? vneg = 50 mv ? two charge pumps for gate driver supply ? cp1: 22 v, 15 ma (vddh) ? cp2: ? 20 v, 15 ma, (vee) ? adjustable vcom driver for accurate panel- backplane biasing ? 0 v to ? 5.11 v ? 1.5% accuracy ( 10 mv) ? 9-bit control (10-mv nominal step size) ? active discharge on all rails ? integrated 10- , 3.3-v power switch for disabling system power rail to e-ink panel 2 applications ? power supply for active matrix e ink vizplex panels ? electronic paper display (epd) power supplies ? e-book readers ? dual-display phone and tablets ? application processors with integrated or software timing controller ( omap ? ) 3 description the tps65185x device is a single-chip power supply designed to for e ink vizplex displays used in portable e-reader applications, and the device supports panel sizes up to 9.7 inches and greater. two high efficiency dc-dc boost converters generate 16-v rails that are boosted to 22 v and ? 20 v by two change pumps to provide the gate driver supply for the vizplex panel. two tracking ldos create the 15-v source driver supplies that support up to 120/200 ma (tps65185/tps651851) of output current. all rails are adjustable through the i 2 c interface to accommodate specific panel requirements. device information (1) part number package body size (nom) tps65185 rgz (48) 7.00 mm 7.00 mm rsl (48) 6.00 mm 6.00 mm tps651851 rsl (48) 6.00 mm 6.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application schematic vin i/o control from input supply (3 v to 6 v) temperature sensor ts dcdc2 vn vn_sw dcdc1 vb_sw vb from input supply (3 v to 6 v) vddh_d vddh_drv vddh_fb positive charge pump vpos ldo1 vee_d vee_drv vee_fb negative charge pump vcom vcom vcom_panel vneg ldo2 vcom productfolder ordernow technical documents tools & software support &community
2 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ......................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 5 7.1 absolute maximum ratings ...................................... 5 7.2 esd ratings .............................................................. 5 7.3 recommended operating conditions ....................... 5 7.4 thermal information .................................................. 6 7.5 electrical characteristics ........................................... 6 7.6 timing requirements: data transmission .............. 10 7.7 typical characteristics ............................................ 12 8 detailed description ............................................ 15 8.1 overview ................................................................. 15 8.2 functional block diagram ....................................... 16 8.3 feature description ................................................. 17 8.4 device functional modes ........................................ 25 8.5 programming ........................................................... 27 8.6 register maps ......................................................... 29 9 application and implementation ........................ 47 9.1 application information ............................................ 47 9.2 typical application ................................................. 47 10 power supply recommendations ..................... 49 11 layout ................................................................... 49 11.1 layout guidelines ................................................. 49 11.2 layout example .................................................... 49 12 device and documentation support ................. 50 12.1 device support ...................................................... 50 12.2 documentation support ........................................ 50 12.3 receiving notification of documentation updates 50 12.4 community resources .......................................... 50 12.5 trademarks ........................................................... 50 12.6 electrostatic discharge caution ............................ 50 12.7 glossary ................................................................ 50 13 mechanical, packaging, and orderable information ........................................................... 50 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from revision d (december 2016) to revision e page ? changed changed the maximum input voltage for tps651851 from 5.9 v to 6 v ................................................................ 5 ? changed the v in range to the v outtol and v diff parameters in the electrical characteristics table ..................................... 7 ? changed the electrostatic discharge caution statement ..................................................................................................... 50 changes from revision c (august 2015) to revision d page ? added tps651851 device to the data sheet .......................................................................................................................... 1 ? added the input voltage range for tps651851 ...................................................................................................................... 1 ? added tps651851 ldo1 and ldo2 current limit of 200 ma ................................................................................................ 1 ? updated the switch current limit to 2.5 a on dcdc1 for tps651851 ................................................................................... 6 ? updated the ldo1 iload current limit for tps651851 ........................................................................................................ 7 ? updated the ldo1 ilimit current limit for tps651851 ........................................................................................................ 7 ? updated the ldo2 iload current range for different vin conditions .................................................................................. 7 ? updated the ldo2 ilimit output current limit to different vin conditions ............................................................................. 7 ? updated the output voltage range (vddh_out) conditions on charge pump 1 .................................................................. 8 ? added the iload current range option for tps651851 on cp1 .......................................................................................... 8 ? added the iload current range option for tps651851 on cp2 .......................................................................................... 8 ? added receiving notification of documentation updates to device and documentation support section ......................... 50 changes from revision b (october 2011) to revision c page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section .................................................................................................. 1
3 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 5 description (continued) accurate back-plane biasing is provided by a linear amplifier that can be adjusted from 0 v to ? 5.11 v with 9-bit control through the serial interface; it can source or sink current depending on panel condition. the tps65185x supports automatic panel kickback voltage measurement, which eliminates the need for manual vcom calibration in the production line. the measurement result can be stored in non-volatile memory to become the new vcom power-up default value. tps65185 is available in two packages, a 48-pin 7-mm 7-mm 2 vqfn (rgz) with 0.5-mm pitch, and a 48-pin 6-mm 6-mm 2 vqfn (rsl) with 0.4-mm pitch. the tps651851 is available in a 48-pin 6-mm 6-mm 2 vqfn (rsl) with 0.4-mm pitch. 6 pin configuration and functions rgz package and rsl package 48-pin vqfn with exposed thermal pad top view pin functions pin i/o description name no. agnd1 8 ? analog ground for general analog circuitry. agnd2 48 ? reference point to external thermistor and linearization resistor. dgnd 6 ? digital ground. connect to ground plane. int 2 o open drain interrupt pin (active low). int_ldo 7 o filter pin for 2.7-v internal supply. n/c 11, 13, 20, 38, 39 ? not internally connected. pbkg 22 ? die substrate. connect to the vn pin ( ? 16 v) with a short, wide trace. a wide copper trace improves heat dissipation. pgnd1 41 ? power ground for dcdc1. pgnd2 32 ? power ground for cp1 (vddh) and cp2 (vee) charge pumps. 36 vddh_drv 1 vref 37 vddh_in 24 pwr_good 35 vddh_d 2 nint 38 n/c 23 pbkg 34 vddh_fb 3 vneg 39 n/c 22 pwrup 33 pgnd2 4 vneg_in 40 vb_sw 21 n/c 32 vee_fb 5 wakeup 41 pgnd1 20 n/c 31 vee_d 6 dgnd 42 vb 19 n/c 30 vee_drv 7 int_ldo 43 vpos_in 18 sda 29 vee_in 8 agnd1 44 vpos 17 scl 28 vn 9 n/c 45 vin3p3 16 vcom_pwr 27 vin_p 10 vin 46 v3p3 15 n/c 26 n/c 11 n/c 47 ts 14 vcom 25 vn_sw 12 vcom_ctrl 48 agnd2 13 n/c not to scale thermal pad
4 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated pin functions (continued) pin i/o description name no. (1) there will be 0-ns of deglitch for pwrx. (2) there will be 62.52- s of deglitch for vcom_ctrl. (3) there will be 93.75- s of deglitch for wakeup. pwr_good 23 o open-drain power good output pin. pin is pulled low when one or more rails are disabled or not in regulation. dcdc1, dcdc2, and vcom have no effect on this pin. (1) pwrup 21 i power-up pin. pull this pin high to power up all output rails. (1) scl 17 i serial interface (i 2 c) clock input. sda 18 i/o serial interface (i 2 c) data input/output. ts 47 i thermistor input pin. connect a 10-k ntc thermistor and a 43-k linearization resistor between this pin and agnd. v3p3 46 o output pin of 3.3-v power switch. vb 42 i feedback pin for boost converter (dcdc1) and supply for vpos ldo and vddh charge pump. vb_sw 40 o boost converter switch out (dcdc1). vcom 15 o filter pin for panel common-voltage driver. vcom_ctrl 12 i vcom enable. pull this pin high to enable the vcom amplifier. when pin is pulled low and vn is enabled, vcom discharge is enabled. (2) vcom_dis 14 i discharge pin for vcom. connect to ground to discharge vcom to ground whenever vcom is disabled. leave floating if discharge function is not desired. vcom_pwr 16 i internal supply input pin to vcom buffer. connect to the output of dcdc2. vddh_d 34 o base voltage output pin for positive charge pump (cp1). vddh_dis 35 i discharge pin for vddh. connect to vddh to discharge vddh to ground whenever the rail is disabled. leave floating if discharge function is not desired. vddh_drv 36 o driver output pin for positive charge pump (cp1). vddh_fb 33 i feedback pin for positive charge pump (cp1). vddh_in 37 i input supply pin for positive charge pump (cp1). vee_d 30 o base voltage output pin for negative charge pump (cp2). vee_dis 29 i discharge pin for vee. connect a resistor from vee _dis to vee to discharge vee to ground whenever the rail is disabled. leave floating if discharge function is not desired. vee_drv 28 o driver output pin for negative charge pump (cp2). vee_fb 31 i feedback pin for negative charge pump (cp2). vee_in 27 i input supply pin for negative charge pump (cp2) (vee). vin 10 i input power supply to general circuitry. vin3p3 45 i input pin to 3.3-v power switch. vin_p 24 i input power supply to inverting buck-boost converter (dcdc2). vn 26 i feedback pin for inverting buck-boost converter (dcdc2) and supply for vneg ldo and vee charge pump. vneg 3 o negative supply output pin for panel source drivers. vneg_dis 9 o discharge pin for vneg. connect to vneg to discharge vneg to ground whenever the rail is disabled. leave floating if discharge function is not desired. vneg_in 4 i input pin for ldo2 (vneg). vn_sw 25 o inverting buck-boost converter switch out (dcdc2). vpos 44 o positive supply output pin for panel source drivers. vpos_dis 19 i discharge pin for vpos. connect a resistor from vpos_dis to vpos to discharge vpos to ground whenever the rail is disabled. leave floating if discharge function is not desired. vpos_in 43 i input pin for ldo1 (vpos). vref 1 o filter pin for 2.25-v internal reference to adc. wakeup 5 i wake up pin (active high). pull this pin high to wake up from sleep mode. ic accepts i 2 c commands after wakeup pin is pulled high but power rails remain disabled until pwrup pin is pulled high. (3) thermal pad ? ? the thermal pad is internally connected to the pbkg pin. connect the thermal pad to the vn pin with a short, wide trace. a wide copper trace improves heat dissipation. do not connect the thermal pad to ground.
5 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) it is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. thermal pad is electrically connected to pbkg, which is supposed to be tied to the output of buck-boost converter. thus wide copper trace in the buck-boost output will help heat dissipated efficiently. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) (2) min max unit input voltage at vin (2) , vin_p, vin3p3 ? 0.3 7 v ground pins to system ground ? 0.3 0.3 v voltage at sda, scl, wakeup, pwrup, vcom_ctrl, vddh_fb, vee_fb, pwr_good, nint ? 0.3 3.6 v voltage on vb, vb_sw, vpos_in, vpos_dis, vddh_in ? 0.3 20 v vddh_dis ? 0.3 30 v voltage on vn, vee_in, vcom_pwr, vneg_dis, vneg_in ? 20 0.3 v voltage from vin_p to vn_sw ? 0.3 30 v voltage on vcom_dis ? 5 0.3 v vee_dis ? 30 0.3 v peak output current internally limited ma continuous total power dissipation 2 w t j operating junction temperature ? 10 125 c t a operating ambient temperature (3) ? 10 85 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 500 7.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit input voltage at vin, vin_p, vin3p3 3 3.7 6 v voltage at sda, scl, wakeup, pwrup, vcom_ctrl, vddh_fb, vee_fb, pwr_good, nint 0 3.6 v t a operating ambient temperature ? 10 85 c t j operating junction temperature ? 10 125 c
6 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 7.4 thermal information thermal metric (1) tps65185 tps651851 unit rgz (vqfn) rsl (vqfn) rsl (vqfn) 48 pins 48 pins 48 pins r ja junction-to-ambient thermal resistance 30 30 30 c/w r jc(top) junction-to-case (top) thermal resistance 15.6 16.2 16.2 c/w r jb junction-to-board thermal resistance 6.6 5.1 5.1 c/w jt junction-to-top characterization parameter 0.2 0.2 0.2 c/w jb junction-to-board characterization parameter 6.6 5.1 5.1 c/w r jc(bot) junction-to-case (bottom) thermal resistance 0.9 0.9 0.9 c/w 7.5 electrical characteristics parameter test conditions min typ max unit input voltage v in input voltage range 3 3.7 6 v v uvlo undervoltage lockout threshold v in falling 2.9 v v hys undervoltage lockout hysteresis v in rising 400 mv input current i q operating quiescent current into v in device switching, no load 5.5 ma i std operating quiescent current into v in device in standby mode 130 a i sleep shutdown current device in sleep mode 3.5 10 a internal supplies vi nt_ldo internal supply 2.7 v c int_ldo nominal output capacitor capacitor tolerance 10% 1 4.7 f v ref internal supply 2.25 v c ref nominal output capacitor capacitor tolerance 10% 3.3 4.7 f dcdc1 (positive boost regulator) v in input voltage range 3 3.7 6 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v out output voltage range 16 v dc set tolerance ? 4.5% 4.5% i out output current 250 ma r ds(on) mosfet on resistance v in = 3.7 v 350 m ? i limit switch current limit (tps65185) 1.5 a switch current limit (tps651851) 2.5 switch current accuracy ? 30% 30% f sw switching frequency 1 mhz l dcdc1 inductor 2.2 h c dcdc1 nominal output capacitor capacitor tolerance 10% 1 2 4.7 f esr output capacitor esr 20 m ? dcdc2 (inverting buck-boost regulator) v in input voltage range 3 3.7 6 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v out output voltage range ? 16 v dc set tolerance ? 4.5% 4.5% i out output current 250 ma
7 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated electrical characteristics (continued) parameter test conditions min typ max unit r ds(on) mosfet on resistance v in = 3.7 v 350 m ? i limit switch current limit 1.5 a switch current accuracy ? 30% 30% l dcdc1 inductor 4.7 h c dcdc1 nominal output capacitor capacitor tolerance 10% 1 3 4.7 f esr capacitor esr 20 m ? ldo1 (vpos) v pos_in input voltage range 15.2 16 16.8 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v set output voltage set value v in = 16 v, vset[2:0] = 0x3h to 0x6h 14.25 15 v v interval output voltage set resolution v in = 16 v 250 mv v outtol output tolerance v set = 15 v, i load = 20 ma, 3 v v in < 5.9 v ? 1% 1% v dropout dropout voltage i load = 120 ma 250 mv v loadreg load regulation ? dc i load = 10% to 90% 1% i load load current range (tps65185) v in 3 v 120 ma load current range (tps651851) 3 v v in < 3.6 v 150 v in 3.6 v 200 i limit output current limit (tps65185) v in 3 v 120 ma output current limit (tps651851) 3 v v in < 3.6 v 150 v in 3.6 v 200 r dis discharge impedance to ground enabled when rail is disabled 800 1000 1200 mismatch to any other rdis ? 2% 2% c ldo1 nominal output capacitor capacitor tolerance 10% 1 4.7 f ldo2 (vneg) v neg_in input voltage range 15.2 16 16.8 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v set output voltage set value v in = ? 16 v vset[2:0] = 0x3h to 0x6h ? 15 ? 14.25 v v interval output voltage set resolution v in = ? 16 v 250 mv v outtol output tolerance v set = ? 15 v, i load = ? 20 ma ? 1% 1% v dropout dropout voltage i load = 120 ma 250 mv v loadreg load regulation ? dc i load = 10% to 90% 1% i load load current range 3 v v in < 3.6 v (tps65185 and tps651851) 120 ma v in 3.6 v (tps65185 and tps651851) 200 i limit output current limit 3 v v in < 3.6 v (tps65185) 180 ma 3 v v in < 3.6 v (tps651851) 158 v in 3.6 v (tps65185 and tps651851) 200 r dis discharge impedance to ground enabled when rail is disabled 800 1000 1200 mismatch to any other rdis ? 2% 2% t ss soft-start time not tested in production 1 ms c ldo2 nominal output capacitor capacitor tolerance 10% 1 4.7 f
8 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated electrical characteristics (continued) parameter test conditions min typ max unit ld01 (pos) and ldo2 (vneg) tracking v diff difference between vpos and vneg v set = 15 v, i load = 20 ma, 0 c to 60 c ambient, 3 v v in < 5.9 v ? 50 50 mv vcom driver i vcom drive current 15 ma v com allowed operating range outside this range vcom is shut down and vcomf interrupt is set ? 5.5 1 v accuracy vcom[8:0] = 0x07dh ( ? 1.25 v), v in = 3.4 v to 4.2 v, no load ? 0.8% 0.8% vcom[8:0] = 0x07dh ( ? 1.25 v), v in = 3 v to 6 v, no load ? 1.5% 1.5% output voltage range ? 5.11 0 v resolution 1lsb 10 mv max number of eeprom writes v com calibration 100 r in input impedance, hiz state hiz = 1 150 m r dis discharge impedance to ground vcom_ctrl = low, hi-z = 0 800 1000 1200 mismatch to any other r dis ? 2% 2% c vcom nominal output capacitor capacitor tolerance 10% 3.3 4.7 f cp1 (vddh) charge pump v ddh_in input voltage range 15.2 16 16.8 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v fb feedback voltage 0.998 v accuracy i load = 2 ma ? 2% 2% v ddh_out output voltage range v set = 22 v, i load = 2 ma, r6 = 1m , r10 = 47.5 k 21 22 23 v v set = 25 v, i load = 2 ma, r6 = 1m , r10 = 41.6 k 24 25 26 v set = 28 v, i load = 2 ma, r6 = 1m , r10 = 37 k 27 28 29 i load load current range (tps65185) 10 ma load current range (tps651851) 15 f sw switching frequency 560 khz r dis discharge impedance to ground enabled when rail is disabled 800 1000 1200 mismatch to any other r dis ? 2% 2% c d driver capacitor 10 nf c o output capacitor 1 2.2 f cp2 (vee) negative charge pump v ee_in input voltage range 15.2 16 16.8 v pg power good threshold fraction of nominal output voltage 90% power good time-out not tested in production 50 ms v fb feedback voltage ? 0.994 v accuracy i load = 2 ma ? 2% 2% v ee_out output voltage range v set = ? 20 v, i load = 3 ma ? 21 ? 20 ? 19 v i load load current range (tps65185) 12 ma load current range (tps651851) 15 f sw switching frequency 560 khz r dis discharge impedance to ground enabled when rail is disabled 800 1000 1200 mismatch to any other r dis ? 2% 2%
9 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated electrical characteristics (continued) parameter test conditions min typ max unit (1) 10-k murata ncp18xh103f03rb thermistor (1%) in parallel with a linearization resistor (43 k , 1%) are used at ts pin for panel temperature measurement. (2) contact factory for 50-ms, 200-ms or 400-ms option. (3) contact ti for alternate address of 0 48h. c d driver capacitor 10 nf c o nominal output capacitor capacitor tolerance 10% 1 2.2 f thermistor monitor (1) a tms temperature to voltage ratio not tested in production ? 0.0161 v/ c offset tms offset temperature = 0 c 1.575 v v tms_hot temp hot trip voltage (t = 50 c) temp_hot_set = 0x8c 0.768 v v tms_cool temp hot escape voltage (t = 45 c) temp_cool_set = 0x82 0.845 v v tms_max maximum input level 2.25 v r ntc_pu internal pullup resistor 7.307 k r linear external linearization resistor 43 k adc res adc resolution not tested in production, 1 bit 16.1 mv adc del adc conversion time not tested in production 19 s tmst tol accuracy not tested in production ? 1 1 lsb logic levels and timing charteristics (scl, sda, pwr_good, pwrx, wakeup) v ol output low threshold level i o = 3 ma, sink current (sda, nint, pwr_good) 0.4 v v il input low threshold level 0.4 v v ih input high threshold level 1.2 v i (bias) input bias current v io = 1.8 v 1 a t deglitch deglitch time, wakeup pin not tested in production 500 s deglitch time, pwrup pin not tested in production 400 t discharge discharge delay not tested in production 100 (2) ms f scl scl clock frequency 400 khz i 2 c slave address 7-bit address 0 68h (3) oscillator f osc oscillator frequency 9 mhz frequency accuracy t a = ? 40 c to 85 c ? 10% 10% thermal shutdown t shtdwn thermal trip point 150 c thermal hysteresis 20 c
10 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 7.6 timing requirements: data transmission v bat = 3.6 v 5%, t a = 25 o c, c l = 100 pf (unless otherwise noted) min nom max unit f (scl) serial clock frequency 100 400 khz t hd;sta hold time (repeated) start condition. after this period, the first clock pulse is generated. scl = 100 khz 4 s scl = 400 khz 600 ns t low low period of the scl clock scl = 100 khz 4.7 s scl = 400 khz 1.3 t high high period of the scl clock scl = 100 khz 4 s scl = 400 khz 600 ns t su;sta set-up time for a repeated start condition scl = 100 khz 4.7 s scl = 400 khz 600 ns t hd;dat data hold time scl = 100 khz 0 3.45 s scl = 400 khz 0 900 ns t su;dat data set-up time scl = 100 khz 250 ns scl = 400 khz 100 t r rise time of both sda and scl signals scl = 100 khz 1000 ns scl = 400 khz 300 t f fall time of both sda and scl signals scl = 100 khz 300 ns scl = 400 khz 300 t su;sto set-up time for stop condition scl = 100 khz 4 s scl = 400 khz 600 ns t buf bus free time between stop and start condition scl = 100 khz 4.7 s scl = 400 khz 1.3 t sp pulse width of spikes that must be suppressed by the input filter scl = 100 khz n/a n/a ns scl = 400 khz 0 50 c b capacitive load for each bus line scl = 100 khz 400 pf scl = 400 khz 400 figure 1. i 2 c data transmission timing t f t hd;sta t low t r t hd;dat t su;dat t high t su;sta t hd;sta t sp t su;sto t r t buf t f s s r s p sda scl
11 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated minimum delay time between wakeup rising edge and ic ready to accept i 2 c transaction. in this example, the first power-up sequence is started by pulling the pwrup pin high (rising edge). power-down is initiated by pulling the wakeup pin low (device enters sleep mode). the second power-up sequence is initiated by pulling the wakeup pin high while the pwrup pin is also high (power up from sleep to active). figure 2. power-up and power-down timing diagram vin pwrup wakeup vneg vee vpos vddh pwr _good vn vb 1.8ms ddly2 ddly3 ddly4 ddly1 300us max) ( standby active sleep active udly2 udly3 udly1 udly4 i2c 300us max) ( udly2 udly1 udly4 udly3 50ms
12 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 7.7 typical characteristics figure 3. default power-up sequence figure 4. default power-down sequence v in = 3.7 v c in = 100 f figure 5. inrush current v in = 5 v c in = 100 f figure 6. inrush current v in = 3 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 7. switching waveforms, vn v in = 3 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 8. switching waveforms, vb
13 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated typical characteristics (continued) v in = 3.7 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 9. switching waveforms, vn v in = 3.7 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 10. switching waveforms, vb v in = 5 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 11. switching waveforms, vn v in = 5 v r load, vpos = 330 r load, vneg = 330 no load on vddh, vee figure 12. switching waveforms, vb v in = 3.7 v i load, v3p3 = 10 ma figure 13. 3p3v switch impedance v in = 3.7 v figure 14. source driver supply tracking -5 0 -4 0 -3 0 -2 0 -1 0 0 1 0 2 0 3 0 4 0 5 0 0 25 50 75 100 125 1 50 1 75 c u rre n t [m a] vpos + vneg[mv] ipo s = ine g ipo s s we ep, in e g= 15m a ipo s = 15m a , in eg s w eep 0 5 10 15 20 25 1 1.5 2 2.5 3 3.5 4 vin3p3[v] r[ ], (vin3p3-v3p3)/10ma w
14 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated typical characteristics (continued) v in = 3.7 v r load, vcom = 1 k figure 15. vcom integrated non-linearity v in = 3.7 v r load, vcom = 1 k figure 16. vcom differential non-linearity v in = 3.7 v figure 17. kickback voltage measurement error v in = 3.7 v avg[1:0] = 00 (single measurement) time from acq bit set to acqc interrupt received figure 18. kickback voltage measurement timing v in = 3.7 v avg[1:0] = 11 (eight measurements) time from acq bit set to acqc interrupt received figure 19. kickback voltage measurement timing -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 640 12 80 192 0 2560 3200 3840 44 80 512 0 f o rce d kick ba c k vo lta g e [m v] measurementerror [lsb] -5 -4 -3 -2 -1 0 1 2 3 4 5 0 64 128 192 25 6 320 384 44 8 512 vc o m c od e inl [mv] -0.2 -0 .15 -0.1 -0 .05 0 0 .05 0.1 0 .15 0.2 0 6 4 12 8 1 92 2 56 3 20 384 448 512 v co m c od e dnl[lsb]
15 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8 detailed description 8.1 overview the tps65185x device provides two adjustable ldos, inverting buck-boost converter, boost converter, thermistor monitoring, and flexible power-up and power-down sequencing. the system can be supplied by a regulated input voltage ranging from 3 v to 6 v. the device is characterized across a ? 10 c to 85 c temperature range, best suited for personal electronic applications. the i 2 c interface provides comprehensive features for using the tps65185x. all rails can be enabled or disabled. power-up and power-down sequences can also be programmed through the i 2 c interface, as well as thermistor configuration and interrupt configuration. voltage adjustment can also be controlled by the i 2 c interface. the adjustable ldos can supply up to 120 ma (tps65185) and 200 ma (tps651851) of current. the default output voltages for each ldo can be adjusted through the i 2 c interface. ldo1 (vpos) and ldo2 (vneg) track each other in a way that they are of opposite sign but same magnitude. the sum of vldo1 and vlod2 is specified to be less than 50 mv. there are two charge pumps: where vddh and vee are 10 ma and 12 ma (tps65185) and vddh and vee are 15 ma and 15 ma (tps651851) respectively. these charge pumps boost the dc-dc boost converters 16-v rails to provide a gate channel supply. the power good functionality is open-drain output, if any of the four power rails (cp1, cp2, ldo1, ldo2) are not in regulation, encounters a fault, or is disabled the pin is pulled low. pwr_good remains low if one of the rails is not enabled by the host and only after all rails are in regulation pwr_good is released to hiz state (pulled up by external resistor). the tps65185x provides circuitry to bias and measure an external ntc to monitor the display panel temperature in a range from ? 10 c to 85 c with and accuracy of 1 c from 0 c to 50 c. temperature measurement are triggered by the controlling host and the last temperature reading is always stored in the tmst_value register. interrupts are issued when the temperature exceeds the programmable hot, or drops below the programmable cold threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value. this device has the following two package options: ? tps65185: 48-pin, 0.5-mm pitch, 7 mm 7 mm 0.9 mm (qfn) rgz ? tps65185 and tps651851: 48-pin, 0.4 mm pitch, 6 mm 6 mm 0.9 mm (qfn) rsl
tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com 16 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.2 functional block diagram figure 20. functional block diagram - tps65185 dcdc2 vin_p 10uf 4.7uf vpos 10nf 2.2uf 1m 52.3k vee_d vee_drv vee_fb 4.7uh vn_sw from battery (3.0v-6.0v) vee (-20v) vpos (15v) dcdc1 4.7uf 2.2uh pgnd1 vb_sw 10uf 10nf 2.2uf 1m 47.5k vddh_d vddh_drv vddh_fb from battery (3.0v-6.0v) vddh (22v) vddh_en vee_en pgnd2 pgnd2 vpos_en vb ldo1 vee charge pump vnpbkg pgnd2 4.7uf vneg_in vddh_in vneg vneg (-15v) vneg_en ldo2 powerpad? temp sensor 43k 10k ntc ts agnd2 adc tmst_value[7:0] 4.7uf 4.7uf vpos_in vin 10uf vcom_pwr 4.7uf from input supply (3.0v-6.0v) 4.7uf vref agnd1 dac vcom vcom[8:0] vcom_ctrl 4.7uf from uc vref 4.7uf int_ldo int_ldo vee_in vddh charge pump 4.7uf 3.3v supply from system to epd panel vin3p3 v3p3 gate driver v3p3_en 1k scl from uc from/to uc or dsp sda 10k vio pwr_good 10k vio digital core wakeup int 10k vio 10k vio from uc pwrup from uc to uc to uc dgnd 100n 100n to panel back -plane (0 to -5.11 v)
17 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.3 feature description 8.3.1 wake-up and power-up sequencing the power-up and power-down order and timing is defined by user register settings. the default settings support the e ink vizplex panel and typically do not need to be changed. in sleep mode the tps65185x is completely turned off, the i 2 c registers are reset, and the device does not accept any i 2 c transaction. pull the wakeup pin high with the pwrup pin low and the device enters standby mode which enables the i 2 c interface. write to the upseq0 register to define the order in which the output rails are enabled at power-up and to the upseq1 registers to define the power-up delays between rails. finally, set the active bit in the enable register to 1 to execute the power-up sequence and bring up all power rails. alternatively pull the pwrup pin high (rising edge). after the active bit has been set, the negative boost converter (vn) is powered up first, followed by the positive boost (vb). the positive boost enable is gated by the internal power-good signal of the negative boost. once vb is in regulation, it issues an internal power-good signal and after delay time udly1 has expired, strobe1 is issued. the rail assigned to strobe1 will power up next and after its power-good signal has been asserted and delay time udly2 has expired, strobe2 is issued. the sequence continues until strobe4 has occurred and the last rail has been enabled. to power down the device, set the standby bit of the enable register to 1 or pull the pwrup pin low (falling edge) and the tps65185x will power down in the order defined by dwnseqx registers. the delay times ddly2, ddly3, and ddly4 are weighted by a factor of dfctr which allows the user to space out the power down of the rails to avoid crossing during discharge. dfctr is located in register dwnseq1. the positive boost (vb) is shut down together with the last rail at strobe4. however, the negative boost (vn) remains up and running for another 100 ms (discharge delay) to allow complete discharge of all rails. after the discharge delay, vn is powered down and the device enters standby or sleep mode, depending on the wakeup pin. if either the active bit is set or the pwrup pin is pulled high while the device is powering down, the power- down sequence (strobe1-4) is completed first, followed by a power-up sequence. vb and vn may or may not be powered down and the discharge delay may be cut short depending on the relative timing of strobe4 to the new power-up event. during power-up, if the standby bit is set or the pwrup pin is pulled low, the power-up sequence is aborted and the power-down sequence starts immediately. 8.3.2 dependencies between rails charge pumps, ldos, and vcom driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. these dependencies are listed below. ? inverting buck-boost (dcdc2) must be in regulation before positive boost (dcdc1) can be enabled. internally, dcdc1 enable is gated by dcdc2 power good. ? positive boost (dcdc1) must be in regulation before ldo2 (vneg) can be enabled. internally ldo2 enable is gated dcdc1 power-good. ? positive boost (dcdc1) must be in regulation before vcom can be enabled. internally vcom enable is gated by dcdc1 power good. ? positive boost (dcdc1) must be in regulation before negative charge pump (cp2) can be enabled. internally cp2 enable is gated by dcdc1 power good. ? positive boost (dcdc1) must be in regulation before positive charge pump (cp1) can be enabled. internally cp1 enable is gated by dcdc1 power good. ? ldo2 must be in regulation before ldo1 can be enabled. internally ldo1 enable is gated by ldo2 power good.
18 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) top: power-up sequence is defined by assigning strobes to individual rails. strobe1 is the first strobe to occur after active bit is set and strobe4 is the last event in the sequence. strobes are assigned to rails in upseq0 register and delays between strobes are defined in upseq1 register. bottom: power-down sequence is independent of power-up sequence. strobes and delay times for power down sequence are set in dwnseq0 and dwnseq1 register. figure 21. power-up and power-down sequence 8.3.3 soft start tps65185x supports soft start for all rails, that is, inrush current is limited during startup of dcdc1, dcdc2, ldo1, ldo2, cp1 and cp2. if dcdc1 or dcdc2 are unable to reach power-good status within 50 ms, the corresponding uv flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters standby mode. ldo1, ldo2, positive and negative charge pumps also have a 50-ms power-good time-out limit. if either rail is unable to power up within 50 ms after it has been enabled, the corresponding uv flag is set and the interrupt pin is pulled low. however, the device will remain in active mode in this case. 8.3.4 active discharge tps65185x provides low-impedance discharge paths for the display power rails (vee, vneg, vpos, vddh, and vcom) which are enabled whenever the corresponding rail is disabled. the discharge paths are connected to the rails on the pcb which allows adding external resistors to customize the discharge time. however, external resistors are not required. udly1 active bit or wakeup high vn pg vb pg udly2 pg1 strobe 1 strobe 2 udly3 pg2 strobe 3 udly4 pg3 strobe 4 pg4 standby bit or wakeup low strobe 2 strobe 1 ddly1 ddly2 ddly3 strobe 3 strobe 4 ddly4 discharge delay vb powers up 1 st rail powers up 2 nd rail powers up 3 nd rail powers up 4 th rail powers up 4 th rail powers down 3 nd rail powers down 2 nd rail powers down 1 st rail powers down vb powers down vn powers down vn powers up
19 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) active discharge remains enabled for 100 ms after the last rail has been disabled (strobe4 has been executed). during this time the negative boost converter (vn) remains up. after the discharge delay, vn is shut down and the device enters standby or sleep mode, depending on the state of the wakeup pin. 8.3.5 vpos/vneg supply tracking ldo1 (vpos) and ldo2 (vneg) track each other in a way that they are of opposite sign but same magnitude. the sum of vldo1 and vlod2 is specified to be < 50 mv. 8.3.6 v3p3 power switch the integrated power switch is used to cut the 3.3-v supply to the epd panel and is controlled through the v3p3_en pin of the enable register. in sleep mode the switch is automatically turned off and its output is discharged to ground. the default power-up state is off. to turn the switch on, set the v3p3_enbit to 1. 8.3.7 vcom adjustment vcom is the output of a power-amplifier with an output voltage range of 0 v to ? 5.11 v, adjustable in 10-mv steps. in a typical application vcom is connected to the vcom terminal of the epd panel and the amplifier is controlled through the vcom_ctrl pin. with vcom_ctrl high, the amplifier drives the vcom pin to the voltage specified by the vcom1 and vcom2 register. when pulled low, the amplifier turns off and vcom is actively discharged to ground through vcom_dis pin. if active discharge is not desired, simply leave the vcom_dis pin open. for ease of design, the vcom_ctrl pin may also be tied to the battery or io supply. in this case, vcom is enabled with strobe4 during the power-up sequence and disabled on strobe1 of the power-down sequence. therefore vcom is the last rail to be enabled and the first to be disabled. 8.3.7.1 kick-back voltage measurement tps65185x can perform a voltage measurement on the vcom pin to determine the kick-back voltage of the panel. this allows in-system calibration of vcom. to perform a kick-back voltage measurement, follow these steps: ? pull the wakeup pin and the pwrup pin high to enable all output rails. ? set the hiz bit in the vcom2 register. this puts the vcom pin in a high-impedance state. ? drive the panel with the null waveform. refer to e-ink specification for detail. ? set the acq bit in the vcom2 register to 1. this starts the measurement routine. ? when the measurement is complete, the acqc (acquisition complete) bit in the int1 register is set and the nint pin is pulled low. ? the measurement result is stored in the vcom[8:0] bits of the vcom1 and vcom2 register. the measurement result is not automatically programmed into nonvolatile memory. changing the power-up default is described in the following paragraph.
20 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) 8.3.7.2 storing the vcom power-up default value in memory the power-up default value of vcom can be user-set and programmed into nonvolatile memory. to do so, write the default value to the vcom[8:0] bits of the vcom1 and vcom2 register, then set the prog bit in vcom2 register to 1. first, all power rails are shut down, then the vcom[8:0] value is committed to nonvolatile memory such that it becomes the new power-up default. once programming is complete, the prgc bit in the int1 register is set and the nint pin is pulled low. to verify that the new value has been saved properly, first write the vcom[8:0] bits to 0x000h, then pull the wakeup pin low. after the wakeup pin is pulled back high, read the vcom[8:0] bits to verify that the new default value is correct. figure 22. block diagram of vcom circuit vin 10 f vcom_pwr 4.7 f to panel back-plane (C0.5 v to 5 v, 15 ma) C from input supply (3 v to 6 v) 4.7 f vref agnd1 dac vcom vcom[8:0] vcom_ctrl 4.7 f from uc vref 4.7 f int_ldo int_ldo from vn (C17 v)
21 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) figure 23. vcom calibration flow pull wakeup = high pull pwrup= high write hiz = 1 device enters active mode all power rails are up except vcom vcom pin is in hiz state processor drives panel with null waveform write acq = 1 starts a/d conversion wait for acqc interrupt indicates a/d conversion is complete if avg[1:0] is <> 00, interrupt is issed after all conversions are complete and average has been calcutated. read result from vcom1/2 registers pull pwrup= low write hiz = 0 check result and decide to keep the value or repeat measurment. device enters standby mode write prog= 1 starts the eeprom programming cycle. power must not be interrupted. wait for prgc interrupt indicates programming is complete pull wakeup = low device enters sleep mode pull wakeup = high device enters standby mode read vcom[8:0] compare against written value toconfirm new default has been programmed correctly. setup measurement programming verification
22 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) 8.3.8 fault handling and recovery the tps65185x monitors input/output voltages and die temperature. the device will take action if operating conditions are outside normal limits when the following is encountered: ? thermal shutdown (tsd) ? positive boost under voltage (vb_uv) ? inverting buck-boost under voltage (vn_uv) ? input undervoltage lockout (uvlo) it shuts down all power rails and enters standby mode. shut-down follows the order defined by dwnseqx registers. the exception is vcom fault witch leads to immediate shutdown of all rails. once a fault is detected, the pwr_good and nint pins are pulled low and the corresponding interrupt bit is set in the interrupt register. power rails cannot be re-enabled unless the interrupt bits have been cleared by reading the int1 and int2 register. alternatively, toggling the wakeup pin also resets the interrupt bits. as the pwrup input is edge sensitive, the host must toggle the pwrup pin to re-enable the rails through gpio control, i.e. it must bring the pwrup pin low before asserting it again. alternatively rails can be re-enabled through the i 2 c interface. whenever the tps65185x encounters undervoltage on vneg (vneg_uv), vpos (vpos_uv), vee (vee_uv) or vddh (vddh_uv), rails are not shut down but the pwr_good and nint is pulled low with the corresponding interrupt bit set. the device remains in active mode and recovers automatically once the fault has been removed. 8.3.9 power good pin the power good pin (pwr_good) is an open-drain output that is pulled high (by an external pullup resistor) when all four power rails (cp1, cp2, ldo1, ldo2) are in regulation and is pulled low if any of the rails encounters a fault or is disabled. pwr_good remains low if one of the rails is not enabled by the host and only after all rails are in regulation pwr_good is released to hiz state (pulled up by external resistor). 8.3.10 interrupt pin the interrupt pin (nint) is an open drain output that is pulled low whenever one or more of the int1 or int2 bits are set. the nint pin is released (returns to hiz state) and fault bits are cleared once the register with the set bit has been read by the host. if the fault persists, the nint pin will be pulled low again after a maximum of 32 s. interrupt events can be masked by resetting the corresponding enable bit in the int_en1 and int_en2 register, that is, the user can determine which events cause the nint pin to be pulled low. the status of the enable bits affects the nint pin only and has no effect on any of the protection and monitoring circuits or the int1/int2 bits themselves. persisting faults such as thermal shutdown can cause the nint pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. if this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the int1 and int2 register to see when the fault condition has disappeared. after the fault is resolved, unmask the interrupt bit again. 8.3.11 panel temperature monitoring the tps65185x provides circuitry to bias and measure an external negative temperature coefficient resistor (ntc) to monitor the display panel temperature in a range from ? 10 c to 85 c with and accuracy of 1 c from 0 c to 50 c. temperature measurement must be triggered by the controlling host and the last temperature reading is always stored in the tmst_value register. interrupts are issued when the temperature exceeds the programmable hot, or drops below the programmable cold threshold, or when the temperature has changed by more than a user-defined threshold from the baseline value. details are explained in hot, cold, and temperature-change interrupts .
23 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated feature description (continued) 8.3.11.1 ntc bias circuit figure 24 below shows the block diagram of the ntc bias and measurement circuit. the ntc is biased from an internally generated 2.25-v reference voltage through an integrated 7.307-k bias resistor. a 43-k resistor is connected parallel to the ntc to linearize the temperature response curve. the circuit is designed to work with a nominal 10-k ntc and achieves accuracy of 1 c from 0 c to 50 c. the voltage drop across the ntc is digitized by a 10-bit sar adc and translated into an 8-bit two ? s complement by digital per table 1 . table 1. adc output value vs temperature temperature tmst_value[7:0] < ? 10 c 1111 0110 ? 10 c 1111 0110 ? 9 c 1111 0111 ... ... ? 2 c 1111 1110 ? 1 c 1111 1111 0 c 0000 0000 1 c 0000 0001 2 c 0000 0010 ... ... 25 c 0001 1001 ... 85 c 0101 0101 > 85 c 0101 0101 figure 24. ntc bias and measurement circuit a temperature measurement is triggered by setting the read_therm bit of the tmst1 register to 1.during the a/d conversion the conv_end bit of the tmst1 register reads 0, otherwise it reads 1. at the end of the a/d conversion the eoc bit in the int2 register is set and the temperature value is available in the tmst_value register. 7.307k 2.25v 43k 10k ntc 10 adc digital ts agnd2
24 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.3.11.2 hot, cold, and temperature-change interrupts each temperature acquisition is compared against the programmable tmst_hot and tmst_cold thresholds and to the baseline temperature, to determine if the display is within allowed operating temperature range and if the temperature has changed by more than a user-defined threshold since the last update. the first temperature reading after the wakeup pin has been pulled high automatically becomes the baseline temperature. any subsequent reading is compared against the baseline temperature. if the difference is equal or greater than the threshold value, an interrupt is issued (dtx bit in register int1 is set to 1) and the latest value becomes the new baseline. if the difference is less than the threshold value, no action is taken. the threshold value is defined by dt[1:0] bits in the tmst1 register and has a default value of 2 c. in summary: ? when the temperature is equal or less than the tmst_cold[3:0] threshold, the tmst_cold interrupt bit of the int1 register is set, and the nint pin is pulled low. ? when the temperature is greater than tmst_cold but lower then tmst_hot, no action is taken. ? when the temperature is equal or greater than the tmst_hot[3:0] threshold, the tmst_hot interrupt bit of the int1 register is set, and the nint pin is pulled low. ? if the last temperature is different from the baseline temperature by 2 c (default) or more, the dtx interrupt bit of the int1 register is set. the latest temperature becomes the new baseline temperature. by default the dtx interrupt is disabled, that is, the nint pin is not pulled low unless the dtx_en bit was previously set high. ? if the last temperature change is less than 2 c (default), no action is taken. 8.3.11.3 typical application of the temperature monitor in a typical application the temperature monitor and interrupts are used in the following manner: ? after the wakeup pin has been pulled high, the application processor (ap) writes 0x80h to the tmst1 register (address 0x0dh). this starts the temperature measurement. ? the ap waits for the eoc interrupt. alternatively the ap can poll the conv_end bit in register tmst1. this will notify the ap that the a/d conversion is complete and the new temperature reading is available in the tmst_value register (address (0x00h). ? the ap reads the temperature value from the tmst_value register (address (0x00h). ? if the temperature changes by 2 c (default) or more from the first reading, the processor is notified by the dtx interrupt. the a/p may or may not decide to select a different set of wave forms to drive the panel. ? if the temperature is outside the allowed operating range of the panel, the processor is notified by the thot and tcold interrupts, respectively. it may or may not decide to continue with the page update. ? once an overtemperature or undertemperature has been detected, the ap must reset the tmst_hot_en or tmst_cold_en bits, respectively, to avoid the nint pin to be continuously pulled low. the tmst_hot and tmst_cold interrupt bits then must be polled continuously, to determine when the panel temperature recovers to the normal operating range. once the temperature has recovered, the tmst_hot_en or tmst_cold_en bits must be set to 1 again and normal operation can resume.
25 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.4 device functional modes the tps65185x has three modes of operation, sleep, standby, and active. sleep mode is the lowest- power mode in which all internal circuitry is turned off. in standby, all power rails are shut down but the device is ready to accept commands through the i 2 c interface. in active mode one or more power rails are enabled. 8.4.1 sleep this is the lowest power mode of operation. all internal circuitry is turned off, registers are reset to default values and the device does not respond to i 2 c communications. tps65185x enters sleep mode whenever wakeup pin is pulled low. 8.4.2 standby in standby all internal support circuitry is powered up and the device is ready to accept commands through the i 2 c interface but none of the power rails are enabled. the device enters standby mode when the wakeup pin is pulled high and either the pwrup pin is pulled low or the standby bit is set. the device also enters standby mode if input uvlo, positive boost undervoltage (vb_uv), or inverting buck-boost undervoltage (vn_uv) is detected, thermal shutdown occurs, or the prog bit is set (see figure 23 ). 8.4.3 active the device is in active mode when any of the output rails are enabled and no fault condition is present. this is the normal mode of operation while the device is powered up. 8.4.4 mode transitions 8.4.4.1 sleep active wakeup pin is pulled high with pwrup pin high. rails come up in the order defined by the upseqx registers (ok to tie wakeup and pwrup pin together). 8.4.4.2 sleep standby wakeup pin is pulled high with pwrup pin low. rails will remain powered down. 8.4.4.3 standby active wakeup pin is high and pwrrup pin is pulled high (rising edge) or the active bit is set. output rails will power up in the order defined by the upseqx registers. 8.4.4.4 active standby wakeup pin is high and standby bit is set or pwrup pin is pulled low (falling edge). rails are shut down in the order defined by dwnseqx registers. device also enters standby in the event of thermal shutdown (tsd), uvlo, positive boost or inverting buck-boost undervoltage (uv), vcom fault (vcomf), or when the prog bit is set (see figure 23 ). 8.4.4.5 standby sleep wakeup pin is pulled low while none of the output rails are enabled. 8.4.4.6 active sleep wakeup pin is pulled low while at least one output rail is enabled. rails are shut down in the order defined by dwnseqx registers.
26 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated device functional modes (continued) notes: ||, & = logic or, and and. ( ), ( ) = rising edge, falling edge uvlo = undervoltage lockout tsd = thermal shutdown uv = undervoltage fault = uvlo || tsd || boost uv || vcom fault figure 25. global state diagram sleep active rails = on i2c = yes power down wakeup = high & pwrup= low all rails = off v3p3 switch = off i2c = no registers default battery removed standby wakeup = high & (active bit = 1 || pwrup( ) ) all rails = off i2c = yes wakeup = high & (standby bit = 1|| pwrup( ) || fault ) wakeup = low wakeup = high & pwrup = high wakeup = low
27 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.5 programming 8.5.1 i 2 c bus operation the tps65185x hosts a slave i 2 c interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to i 2 c standard 3.0. figure 26. subaddress in i 2 c transmission the i 2 c bus is a communications link between a controller and a series of slave terminals. the link is established using a two-wire bus consisting of a serial clock signal (scl) and a serial data signal (sda). the serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. each device has an open drain output to transmit data on the serial data line. an external pullup resistor must be placed on the serial data line to pull the drain output high during data transmission. data transmission is initiated with a start bit from the controller as shown in figure 28 . the start condition is recognized when the sda line transitions from high to low during the high portion of the scl signal. upon reception of a start bit, the device will receive serial data on the sda input and check for valid address and control information. if the appropriate slave address bits are set for the device, then the device will issue an acknowledge pulse and prepare to receive the register address. depending on the r/nw bit, the next byte received from the master is written to the addressed register (r/nw = 0) or the device responds with 8-bit data from the register (r/nw = 1). data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. a stop condition is recognized as a low to high transition of the sda input during the high portion of the scl signal. all other transitions of the sda line must occur during the low portion of the scl signal. an acknowledge is issued after the reception of valid address, sub-address, and data words. the i 2 c interfaces will auto-sequence through register addresses, so that multiple data words can be sent for a given i 2 c transmission. see figure 27 and figure 28 for details. s a6 a5 a4 a3 a2 a1 a0 a s7 s6 s5 s4 s3 s2 s1 s0 a d7 d6 d5 d4 d3 d2 d1 d0 a p s a start condition acknowledge a6 a0 ... device address r/nw read / not write s7 s0 ... sub-address d7 d0 ... data p stop condition r/nw slave address + r/nw reg address data
28 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated programming (continued) top: master writes data to slave. bottom: master reads data from slave. figure 27. i 2 c data protocol figure 28. i 2 c start/stop/acknowledge protocol s 1-7 8 9 1-7 8 9 1-7 8 9 p address r/w ack data ack data ack/ nack stop start sda scl slave address w a reg address a slave address r a data regaddr a s data regaddr +n a data regaddr + n+1 p from master to slavefrom slave to master s w a p start write (low) acknowlege stop r read (high) s not acknowlege n bytes + ack slave address w a reg address a data regaddr a s data subaddr +n a data subaddr +n+1 p n bytes + ack
29 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6 register maps table 2. register address map address acronym register name section 0x00h tmst_value thermistor value read by adc go 0x01h enable enable/disable bits for regulators go 0x02h vadj vpos/vneg voltage adjustment go 0x03h vcom1 voltage settings for vcom go 0x04h vcom2 voltage settings for vcom + control go 0x05h int_en1 interrupt enable group1 go 0x06h int_en2 interrupt enable group2 go 0x07h int1 interrupt group1 go 0x08h int2 interrupt group2 go 0x09h upseq0 power-up strobe assignment go 0x0ah upseq1 power-up sequence delay times go 0x0bh dwnseq0 power-down strobe assignment go 0x0ch dwnseq1 power-down sequence delay times go 0x0dh tmst1 thermistor configuration go 0x0eh tmst2 thermistor hot temp set go 0x0fh pg power good status each rails go 0x10h revid device revision id information go 8.6.1 thermistor readout (tmst_value) register (address = 0x00h) [reset = n/a] figure 29. tmst_value register 7 6 5 4 3 2 1 0 tmst_value[7:0] r-n/a legend: r/w = read/write; r = read only; -n = value after reset table 3. tmst_value register field descriptions bit field type reset description 7-0 tmst_value r n/a temperature read-out f6h = < ? 10 c f7h = ? 9 c ... feh = ? 2 c ffh = ? 1 c 0h = 0 c 1h = 1 c 2h = 2 c ... 19h = 25 c ... 55h = > 85 c
30 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.2 enable (enable) register (address = 0x01h) [reset = 0h] figure 30. enable register 7 6 5 4 3 2 1 0 active standby v3p3_en vcom_en vddh_en vpos_en vee_en vneg_en r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only; -n = value after reset table 4. enable register field descriptions bit field type reset description 7 active r/w 0h standby to active transition bit 0h = no effect 1h = transition from standby to active mode. rails power up as defined by upseqx registers note: after transition bit is cleared automatically 6 standby r/w 0h standby to active transition bit 0h = no effect 1h = transition from standby to active mode. rails power up as defined by dwnseqx registers note: after transition bit is cleared automatically. standby bit has priority over active. 5 v3p3_en r/w 0h vin3p3 to v3p3 switch enable 0h = switch is off 1h = switch is on 4 vcom_en r/w 0h vcom buffer enable 0h = disabled 1h = enabled 3 vddh_en r/w 0h vddh charge pump enable 0h = disabled 1h = enabled 2 vpos_en r/w 0h vpos ldo regulator enable 0h = disabled 1h = enabled note: vpos cannot be enabled before vneg is enabled. 1 vee_en r/w 0h vee charge pump enable 0h = disabled 1h = enabled 0 vneg_en r/w 0h vneg ldo regulator enable 0h = disabled 1h = enabled note: when vneg is disabled vpos will also be disabled.
31 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.3 voltage adjustment (vadj) register (address = 0x02h) [reset = 23h] figure 31. vadj register 7 6 5 4 3 2 1 0 not used not used not used not used not used vset[2:0] r/w-0h r/w-0h r/w-1h r/w-0h r-0h r/w-3h legend: r/w = read/write; r = read only; -n = value after reset table 5. vadj register field descriptions bit field type reset description 7 not used r/w 0h n/a 6 not used r/w 0h n/a 5 not used r/w 1h n/a 4 not used r/w 0h n/a 3 not used r 0h n/a 2-0 vset r/w 3h vpos and vneg voltage setting 0h = not valid 1h = not valid 2h = not valid 3h = 15.000 v 4h = 14.750 v 5h = 14.500 v 6h = 14.250 v 7h = reserved
32 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.4 vcom 1 (vcom1) register (address = 0x03h) [reset = 7dh] figure 32. vcom1 register 7 6 5 4 3 2 1 0 vcom[7:0] r/w-7dh legend: r/w = read/write; r = read only; -n = value after reset table 6. vcom1 register field descriptions bit field type reset description 7-0 vcom r/w 7dh vcom voltage, least significant byte. see vcom 2 (vcom2) register (address = 0x04h) [reset = 04h] for details.
33 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.5 vcom 2 (vcom2) register (address = 0x04h) [reset = 04h] figure 33. vcom2 register 7 6 5 4 3 2 1 0 acq prog hiz avg[1:0] not used not used vcom[8] r/w-0h r/w-0h r/w-0h r/w-0h r/w-1h r/w-0h r/w-0h legend: r/w = read/write; r = read only; -n = value after reset table 7. vcom2 register field descriptions bit field type reset description 7 acq r/w 0h kick-back voltage acquisition bit 0h = no effect 1h = starts kick-back voltage measurement routine note: after measurement is complete bit is cleared automatically and measurement result is reflected in vcom[8:0] bits. 6 prog r/w 0h vcom programming bit 0h = no effect 1h = vcom[8:0] value is committed to nonvolatile memory and becomes new power-up default note: after programming bit is cleared automatically and tps65185x will enter standby mode. 5 hiz r/w 0h vcom hiz bit 1h = vcom pin is placed into hi-impedance state to allow vcom measurement 0h = vcom amplifier is connected to vcom pin 4-3 avg r/w 0h number of acquisitions that is averaged to a single kick-back voltage measurement 0h = 1x 1h = 2x 2h = 4x 3h = 8x note: when the acq bit is set, the state machine repeat the a/d conversion of the kick-back voltage avd[1:0] times and returns a single, averaged, value to vcom[8:0] 2 not used r/w 1h n/a 1 not used r/w 0h n/a 0 vcom r/w 0h vcom voltage adjustment vcom = vcom[8:0] x ? 10 mv in the range from 0 mv to ? 5.110 v 0h = ? 0 mv 1h = ? 10 mv 2h = ? 20 mv ... 7dh = ? 1250 mv ... 1feh = ? 5100 mv 1ffh = ? 5110 mv
34 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.6 interrupt enable 1 (int_en1) register (address = 0x05h) [reset = 7fh] figure 34. int_en1 register 7 6 5 4 3 2 1 0 dtx_en tsd_en hot_en tmst_hot_e n tmst_cold_ en uvlo_en acqc_en prgc_en r-0h r/w-1h r/w-1h r/w-1h r/w-1h r/w-1h r-1h r-1h legend: r/w = read/write; r = read only; -n = value after reset table 8. int_en1 register field descriptions bit field type reset description 7 dtx_en r 0h panel temperature-change interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 6 tsd_en r/w 1h thermal shutdown interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 5 hot_en r/w 1h thermal shutdown early warning enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 4 tmst_hot_en r/w 1h thermistor hot interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 3 tmst_cold_en r/w 1h thermistor cold interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 2 uvlo_en r/w 1h vin under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 1 acqc_en r 1h vcom acquisition complete interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs.
35 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated table 8. int_en1 register field descriptions (continued) bit field type reset description 0 prgc_en r 1h vcom programming complete interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs.
36 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.7 interrupt enable 2 (int_en2) register (address = 0x06h) [reset = ffh] figure 35. int_en2 register 7 6 5 4 3 2 1 0 vbuven vddhuven vnuv_en vposuven veeuven vcomfen vneguven eocen r/w-1h r/w-1h r/w-1h r/w-1h r/w-1h r/w-1h r/w-1h r/w-1h legend: r/w = read/write; r = read only; -n = value after reset table 9. int_en2 register field descriptions bit field type reset description 7 vbuven r/w 1h positive boost converter under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 6 vddhuven r/w 1h vddh under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 5 vnuv_en r/w 1h inverting buck-boost converter under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 4 vposuven r/w 1h vpos under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 3 veeuven r/w 1h vee under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 2 vcomfen r/w 1h vcom fault interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs. 1 vneguven r/w 1h vneg under voltage detect interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs.
37 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated table 9. int_en2 register field descriptions (continued) bit field type reset description 0 eocen r/w 1h temperature adc end of conversion interrupt enable 0h = disabled 1h = enabled note: enabled means nint pin is pulled low when interrupt occurs. disabled means nint pin is not pulled low when interrupt occurs.
38 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.8 interrupt 1 (int1) register (address = 0x07h) [reset = 0h] figure 36. int1 register 7 6 5 4 3 2 1 0 dtx tsd hot tmst_hot tmst_cold uvlo acqc prgc r-0h r-n/a r-n/a r-n/a r-n/a r-n/a r-0h r-0h legend: r/w = read/write; r = read only; -n = value after reset table 10. int1 register field descriptions bit field type reset description 7 dtx r 0h panel temperature-change interrupt 0h = no significance 1h = temperature has changed by 3 deg or more over previous reading 6 tsd r n/a thermal shutdown interrupt 0h = no fault 1h = chip is in over-temperature shutdown 5 hot r n/a thermal shutdown early warning 0h = no fault 1h = chip is approaching over-temperature shutdown 4 tmst_hot r n/a thermistor hot interrupt 0h = no fault 1h = thermistor temperature is equal or greater than tmst_hot threshold 3 tmst_cold r n/a thermistor cold interrupt 0h = no fault 1h = thermistor temperature is equal or less than tmst_cold threshold 2 uvlo r n/a vin under voltage detect interrupt 0h = no fault 1h = input voltage is below uvlo threshold 1 acqc r 0h vcom acquisition complete 0h = no significance 1h = vcom measurement is complete 0 prgc r 0h vcom programming complete 0h = no significance 1h = vcom programming is complete
39 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.9 interrupt 2 (int2) register (address = 0x08h) [reset = n/a] figure 37. int2 register 7 6 5 4 3 2 1 0 vb_uv vddh_uv vn_uv vpos_uv vee_uv vcomf vneg_uv eoc r-n/a r-n/a r-n/a r-n/a r-n/a r-n/a r-n/a r-n/a legend: r/w = read/write; r = read only; -n = value after reset table 11. int2 register field descriptions bit field type reset description 7 vb_uv r n/a positive boost converter undervoltage detect interrupt 0h = no fault 1h = under-voltage on dcdc1 detected 6 vddh_uv r n/a vddh under voltage detect interrupt 0h = no fault 1h = undervoltage on vddh charge pump detected 5 vn_uv r n/a inverting buck-boost converter under voltage detect interrupt 0h = no fault 1h = undervoltage on dcdc2 detected 4 vpos_uv r n/a vpos undervoltage detect interrupt 0h = no fault 1h = undervoltage on ldo1(vpos) detected 3 vee_uv r n/a vee undervoltage detect interrupt 0h = no fault 1h = undervoltage on vee charge pump detected 2 vcomf r n/a vcom fault detection 0h = no fault 1h = fault on vcom detected (vcom is outside normal operating range) 1 vneg_uv r n/a vneg undervoltage detect interrupt 0h = no fault 1h = undervoltage on ldo2(vneg) detected 0 eoc r n/a adc end of conversion interrupt 0h = no significance 1h = adc conversion is complete (temperature acquisition is complete)
40 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.10 power-up sequence 0 (upseq0) register (address = 0x09h) [reset = e4h] figure 38. upseq0 register 7 6 5 4 3 2 1 0 vddh_up[1:0] vpos_up[1:0] vee_up[1:0] vneg_up[1:0] r/w-3h r/w-2h r/w-1h r/w-0h legend: r/w = read/write; r = read only; -n = value after reset table 12. upseq0 register field descriptions bit field type reset description 7-6 vddh_up r/w 3h vddh power-up order 0h = power up on strobe1 1h = power up on strobe2 2h = power up on strobe3 3h = power up on strobe4 5-4 vpos_up r/w 2h vpos power-up order 0h = power up on strobe1 1h = power up on strobe2 2h = power up on strobe3 3h = power up on strobe4 3-2 vee_up r/w 1h vee power-up order 0h = power up on strobe1 1h = power up on strobe2 2h = power up on strobe3 3h = power up on strobe4 1-0 vneg_up r/w 0h vneg power-up order 0h = power up on strobe1 1h = power up on strobe2 2h = power up on strobe3 3h = power up on strobe4 figure 39. default power-up/down sequence vneg vee vpos vddh 6ms 6ms 48ms 6ms 6ms 6ms
41 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.11 power-up sequence 1 (upseq1) register (address = 0x0ah) [reset = 55h] figure 40. upseq1 register 7 6 5 4 3 2 1 0 udly4[1:0] udly3[1:0] udly2[1:0] udly1[1:0] r/w-1h r/w-1h r/w-1h r/w-1h legend: r/w = read/write; r = read only; -n = value after reset table 13. upseq1 register field descriptions bit field type reset description 7-6 udly4 r/w 1h dly4 delay time set; defines the delay time from strobe3 to strobe4 during power up. 0h = 3 ms 1h = 6 ms 2h = 9 ms 3h = 12 ms 5-4 udly3 r/w 1h dly3 delay time set; defines the delay time from strobe2 to strobe3 during power up. 0h = 3 ms 1h = 6 ms 2h = 9 ms 3h = 12 ms 3-2 udly2 r/w 1h dly2 delay time set; defines the delay time from strobe1 to strobe2 during power up. 0h = 3 ms 1h = 6 ms 2h = 9 ms 3h = 12 ms 1-0 udly1 r/w 1h dly1 delay time set; defines the delay time from vn_pg high to strobe1 during power up. 0h = 3 ms 1h = 6 ms 2h = 9 ms 3h = 12 ms
42 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.12 power-down sequence 0 (dwnseq0) register (address = 0x0bh) [reset = 1eh] figure 41. dwnseq0 register 7 6 5 4 3 2 1 0 vddh_dwn[1:0] vpos_dwn[1:0] vee_dwn[1:0] vneg_dwn[1:0] r/w-0h r/w-1h r/w-3h r/w-2h legend: r/w = read/write; r = read only; -n = value after reset table 14. dwnseq0 register field descriptions bit field type reset description 7-6 vddh_dwn r/w 0h vddh power-down order 0h = power down on strobe1 1h = power down on strobe2 2h = power down on strobe3 3h = power down on strobe4 5-4 vpos_dwn r/w 1h vpos power-down order 0h = power down on strobe1 1h = power down on strobe2 2h = power down on strobe3 3h = power down on strobe4 3-2 vee_dwn r/w 3h vee power-down order 0h = power down on strobe1 1h = power down on strobe2 2h = power down on strobe3 3h = power down on strobe4 1-0 vneg_dwn r/w 2h vneg power-down order 0h = power down on strobe1 1h = power down on strobe2 2h = power down on strobe3 3h = power down on strobe4
43 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.13 power-down sequence 1 (dwnseq1) register (address = 0x0ch) [reset = e0h] figure 42. dwnseq1 register 7 6 5 4 3 2 1 0 ddly4[1:0] ddly3[1:0] ddly2[1:0] ddly1 dfctr r/w-3h r/w-2h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only; -n = value after reset table 15. dwnseq1 register field descriptions bit field type reset description 7-6 ddly4 r/w 3h dly4 delay time set; defines the delay time from strobe3 to strobe4 during power down. 0h = 6 ms 1h = 12 ms 2h = 24 ms 3h = 48 ms 5-4 ddly3 r/w 2h dly3 delay time set; defines the delay time from strobe2 to strobe3 during power down. 0h = 6 ms 1h = 12 ms 2h = 24 ms 3h = 48 ms 3-2 ddly2 r/w 0h dly2 delay time set; defines the delay time from strobe1 to strobe2 during power down. 0h = 6 ms 1h = 12 ms 2h = 24 ms 3h = 48 ms 1 ddly1 r/w 0h dly2 delay time set; defines the delay time from wakeup low to strobe1 during power down. 0h = 3 ms 1h = 6 ms 0 dfctr r/w 0h at power-down delay time dly2[1:0], dly3[1:0], dly4[1:0] are multiplied with dfctr[1:0] 0h = 1x 1h = 16x
44 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.14 thermistor 1 (tmst1) register (address = 0x0dh) [reset = 20h] figure 43. tmst1 register 7 6 5 4 3 2 1 0 read_therm not used conv_end not used not used not used dt[1:0] r/w-0h r/w-0h r-1h r/w-0h r/w-0h r/w-0h r/w-0h legend: r/w = read/write; r = read only; -n = value after reset table 16. tmst1 register field descriptions bit field type reset description 7 read_therm r/w 0h read thermistor value 0h = no effect 1h = initiates temperature acquisition note: bit is self-cleared after acquisition is completed 6 not used r/w 0h not used 5 conv_end r 1h adc conversion done flag 0h = conversion is not finished 1h = conversion is finished 4 not used r/w 0h not used 3 not used r/w 0h not used 2 not used r/w 0h not used 1-0 dt r/w 0h panel temperature-change interrupt threshold 0h = 2 c 1h = 3 c 2h = 4 c 3h = 5 c dtx interrupt is issued when difference between most recent temperature reading and baseline temperature is equal to or greater than threshold value. see hot, cold, and temperature- change interrupts for details.
45 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.15 thermistor 2 (tmst2) register (address = 0x0eh) [reset = 78h] figure 44. tmst2 register 7 6 5 4 3 2 1 0 tmst_cold[3:0] tmst_hot[3:0] r/w-7h r/w-8h legend: r/w = read/write; r = read only; -n = value after reset table 17. tmst2 register field descriptions bit field type reset description 7-4 read_therm r/w 7h thermistor cold threshold 0h = ? 7 c 1h = ? 6 c 2h = ? 5 c 3h = ? 4 c 4h = ? 3 c 5h = ? 2 c 6h = ? 1 c 7h = 0 c 8h = 1 c 9h = 2 c ah = 3 c bh = 4 c ch = 5 c dh = 6 c eh = 7 c fh = 8 c note: an interrupt is issued when thermistor temperature is equal or less than cold threshold 3-0 tmst_hot r/w 8h thermistor hot threshold 0h = 42 c 1h = 43 c 2h = 44 c 3h = 45 c 4h = 46 c 5h = 47 c 6h = 48 c 7h = 49 c 8h = 50 c 9h = 51 c ah = 52 c bh = 53 c ch = 54 c dh = 55 c eh = 56 c fh = 57 c note: an interrupt is issued when thermistor temperature is equal or greater than hot threshold
46 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 8.6.16 power good status (pg) register (address = 0x0fh) [reset = 0h] note: pg pin is pulled hi (hiz state) when vddh_pg = vpos_pg = vee_pg = vneg_pg = 1 figure 45. pg register 7 6 5 4 3 2 1 0 vb_pg vddh_pg vn_pg vpos_pg vee_pg not used vneg_pg not used r-0h r-0h r-0h r-0h r-0h r-0h r-0h r-0h legend: r/w = read/write; r = read only; -n = value after reset table 18. pg register field descriptions bit field type reset description 7 vb_pg r 0h positive boost converter power good 0h = dcdc1 is not in regulation or turned off 1h = dcdc1 is in regulation 6 vddh_pg r 0h vddh power good 0h = vddh charge pump is not in regulation or turned off 1h = vddh charge pump is in regulation 5 vn_pg r 0h inverting buck-boost power good 0h = dcdc2 is not in regulation or turned off 1h = dcdc2 is in regulation 4 vpos_pg r 0h vpos power good 0h = ldo1(vpos) is not in regulation or turned off 1h = ldo1(vpos) is in regulation 3 vee_pg r 0h vee power good 0h = vee charge pump is not in regulation or turned off 1h = vee charge pump is in regulation 2 not used r 0h not used 1 vneg_pg r 0h vneg power good 0h = ldo2(vneg) is not in regulation or turned off 1h = ldo2(vneg) is in regulation 0 not used r 0h not used 8.6.17 revision and version control (revid) register (address = 0x10h) [reset = 45h] figure 46. revid register 7 6 5 4 3 2 1 0 revid[7:0] r-45h legend: r/w = read/write; r = read only; -n = value after reset table 19. revid register field descriptions bit field type reset description 7-0 revid r 45h revid[7:6] = mjrev revid[5:4] = mnrev revid[3:0] = version 45h = tps65185 1p0 55h = tps65185 1p1 65h = tps65185 1p2 66h = tps651851 1p0
47 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the tps65185x device is used to power display screens in e-book applications, specifically e-ink vizplex display, by connecting the screen to the positive and negative charge pump, ldos 1 and 2, and vcom rails. the display screens size that can be supported up to 9.7 inches. 9.2 typical application 9.2.1 design requirements for this design example, use the parameters listed in table 20 as the input parameters. table 20. design parameters voltage sequence (strobe) vneg (ldo2) ? 15 v 1 vee (charge pump 2) ? 20 v 2 vpos (ldo1) 15 v 3 vddh (charge pump 1) 22 v 4 vin i/ o control from input supply (3. 0 v-6. 0 v) temp sensor ts dcdc2 vn vn _sw dcdc1 vb_sw vb from input supply (3. 0 v-6. 0 v) vddh_d vddh_ drv vddh_fb positive charge pump vpos ldo1 vee_d vee_ drv vee_fb negative charge pump vcom vcom vcom_ panel vneg ldo2 vcom
48 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 9.2.2 detailed design procedure use the recommended values listed in . table 21. recommended external components part number value size manufacturer inductors lqh44pn4r7mp0 4.7 h 4 mm 4 mm 1.65 mm murata nr4018t4r7m 4.7 h 4 mm 4 mm 1.8 mm taiyo yuden vls252015et-2r2m 2.2 h 2 mm 2.5 mm 1.5 mm tdk nr4012t2r2m 2.2 h 4 mm 4 mm 1.2 mm taiyo yuden capacitors grm21bc81e475ka12l 4.7 f, 25 v, x6s 805 murata grm32er71h475ka88l 4.7 f, 50 v, x7r 1210 murata all other capacitors x5r or better ? ? diodes bas3010 ? sod-323 infineon mbr130t1 ? sod-123 on-semi bav99 ? sot-23 fairchild thermistor ncp18xh103f03rb 10 k 603 murata 9.2.3 application curves t = 25 c figure 47. vn dcdc efficiency t = 25 c figure 48. vb dcdc efficiency t = 25 c figure 49. vee charge pump efficiency t = 25 c figure 50. vddh charge pump efficiency 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 output current [ma] efficiency [%] vin=5v vin=3.5v 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 output current [ma] efficiency [%] vin=5v vin=3. 5 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 output current [m a] efficiency [%] v in= 3. 5 v in= 5v 0 10 20 30 40 50 60 70 80 90 100 0 25 50 75 100 125 150 175 output current [m a] efficiency [%] vin= 3. 5 vin= 5v
49 tps65185 , tps651851 www.ti.com slvsaq8e ? february 2011 ? revised february 2017 product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 10 power supply recommendations the device is designed to operate with an input voltage supply range from 3 v to 6 v. this input supply can be from a externally regulated supply. if the input supply is located more than a few inches from the tps65185x, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. an electrolytic capacitor with a value of 10 f is a typical choice. 11 layout 11.1 layout guidelines 1. pbkg (die substrate) must connect to vn ( ? 16 v) with short, wide trace. wide copper trace will improve heat dissipation. 2. the thermal pad is internally connected to pbkg and must not be connected to ground, but connected to vn with a short wide copper trace. 3. inductor traces must be kept on the pcb top layer free of any vias. 4. feedback traces must be routed away from any potential noise source to avoid coupling. 5. output caps must be placed immediately at output pin. 6. the vin pins must be bypassed to ground with low esr ceramic bypass capacitors. 11.2 layout example figure 51. layout diagram tps6518x thermal pad bottom layer vn connection
50 tps65185 , tps651851 slvsaq8e ? february 2011 ? revised february 2017 www.ti.com product folder links: tps65185 tps651851 submit documentation feedback copyright ? 2011 ? 2017, texas instruments incorporated 12 device and documentation support 12.1 device support 12.1.1 third-party products disclaimer ti's publication of information regarding third-party products or services does not constitute an endorsement regarding the suitability of such products or services or a warranty, representation or endorsement of such products or services, either alone or in combination with any ti product or service. 12.2 documentation support 12.2.1 related documentation for related documentation see the following: ? tps65185 evaluation module ? understanding undervoltage lockout in display power devices 12.3 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.4 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.5 trademarks omap, e2e are trademarks of texas instruments. vizplex is a trademark of e ink corporation. e ink is a registered trademark of e ink corporation. all other trademarks are the property of their respective owners. 12.6 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps651851rslr active vqfn rsl 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -10 to 85 tps 651851 tps651851rslt active vqfn rsl 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -10 to 85 tps 651851 tps65185rgzr active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 e ink tps65185 tps65185rgzt active vqfn rgz 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 e ink tps65185 tps65185rslr active vqfn rsl 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 tps 65185 tps65185rslt active vqfn rsl 48 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 tps 65185 TPS65185SRGZR active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 e ink tps65185 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps651851rslr vqfn rsl 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 tps651851rslt vqfn rsl 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 tps65185rgzr vqfn rgz 48 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 q2 tps65185rgzt vqfn rgz 48 250 180.0 16.4 7.3 7.3 1.1 12.0 16.0 q2 tps65185rslr vqfn rsl 48 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 tps65185rslt vqfn rsl 48 250 180.0 16.4 6.3 6.3 1.1 12.0 16.0 q2 package materials information www.ti.com 24-jan-2017 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps651851rslr vqfn rsl 48 2500 367.0 367.0 38.0 tps651851rslt vqfn rsl 48 250 210.0 185.0 35.0 tps65185rgzr vqfn rgz 48 2500 367.0 367.0 38.0 tps65185rgzt vqfn rgz 48 250 210.0 185.0 35.0 tps65185rslr vqfn rsl 48 2500 367.0 367.0 38.0 tps65185rslt vqfn rsl 48 250 210.0 185.0 35.0 package materials information www.ti.com 24-jan-2017 pack materials-page 2

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